2023-01-14 / Last updated : 2023-03-11 admin Simulator Vortex: OpenCL Compatible RISC-V Based GPGPU (Part 1) This article introduces an overview of Vortex, an open source RISC-V based GPGPU, and how to run the OpenCL program using the Vortex simulator.
2022-12-31 / Last updated : 2022-12-30 admin Summary Luffca 2022 Wrap-Up This article is Luffca’s 2022 wrap-up. In 2022, we sensed the potential for the RISC-V Vector Extension and the RISC-V Custom Extension.
2022-12-24 / Last updated : 2023-01-25 admin FPGA Matrix Multiplication on FPGA with the RISC-V Vector Extension We have implemented Vicuna, an implementation of the RISC-V Vector Extension, on an FPGA board and evaluated the performance of the matrix multiplication kernel.
2022-12-10 / Last updated : 2023-01-25 admin FPGA OpenMP on FPGA with RISC-V Multi-Core Processor We have implemented a RISC-V multi-core processor on an FPGA board and evaluated the performance of the matrix multiplication kernel using OpenMP.
2022-11-19 / Last updated : 2022-12-10 admin FPGA TensorFlow Lite for Microcontrollers on RISC-V Out-of-Order Core We have successfully run Google’s TensorFlow Lite for Microcontrollers on an FPGA board implementing NaxRiscv, a RISC-V Out-of-Order core.
2022-11-05 / Last updated : 2022-11-04 admin FPGA Applying the Tiny Matrix Extension to ML Inference We have accelerated machine learning (ML) model inference using a RISC-V processor that accelerates matrix multiplication at low resource cost.
2022-10-22 / Last updated : 2023-01-25 admin Simulator 1×1 Convolution based on the RISC-V Vector Extension We have created a 1×1 convolution kernel based on the RISC-V Vector Extension (RVV) and evaluated its performance using an RTL simulator.
2022-10-08 / Last updated : 2022-12-09 admin FPGA Running Dual-Core RISC-V Linux on Cheap FPGA Board We have successfully built a dual-core 32-bit RISC-V SoC for a Sipeed Tang Primer that we purchased for about $20 and run Linux.
2022-09-24 / Last updated : 2022-12-10 admin FPGA Running Debian on FPGA with RISC-V Out-of-Order Core We have successfully built the gateware for RV64GC NaxRiscv, a RISC-V Out-of-Order core, for Digilent FPGA board and run Debian.
2022-09-10 / Last updated : 2023-01-25 admin FPGA Tiny Matrix Extension using RISC-V Custom Instructions We have developed a processor that accelerates matrix multiplication using RISC-V custom instructions, implemented it on an FPGA board, and evaluated its performance.
