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cfu-playground-part2
2022-05-07 / Last updated : 2022-05-06 admin FPGA

Building an ML Accelerator using CFU Playground (Part 2)

We have built a tiny machine learning (TinyML) accelerator on an Arty A7-35T using CFU Playground. In part 2, we have accelerated the inference of the Keyword Spotting model.

benchmark-boom-simulator
2022-04-16 / Last updated : 2022-04-16 admin Simulator

Running CoreMark on SonicBOOM Simulator

We have created a simulator with the short-forwards branch (SFB) optimization of SonicBOOM, an out-of-order execution superscalar RISC-V CPU, and ran CoreMark.

systolic-array
2022-04-02 / Last updated : 2022-04-01 admin Simulator

Running Test Programs on Gemmini Simulators

We built an environment for Chipyard, a RISC-V SoC design framework, created simulators for Gemmini, a DNN accelerator, and ran the test programs gemmini-rocc-tests.

benchmark-naxriscv-simulator
2022-03-19 / Last updated : 2022-04-15 admin Simulator

Running CoreMark on NaxRiscv Simulator

We have created a Verilator simulator for NaxRiscv, an out-of-order (OoO) superscalar RISC-V CPU. We ran CoreMark using the created simulator and confirmed 4.70 CoreMark/MHz as the nominal value of NaxRiscv.

cfu-playground-part1
2022-03-05 / Last updated : 2022-05-06 admin FPGA

Building an ML Accelerator using CFU Playground (Part 1)

We have built a machine learning (ML) accelerator on an Arty A7-35T using CFU Playground. In part 1, we have accelerated the inference of the Person Detection int 8 model.

benchmark-linux-litex-rocket
2022-02-19 / Last updated : 2022-03-19 admin FPGA

Benchmarks in LiteX/Rocket on FPGA boards

We measured a performance of the multi-core 64-bit Rocket Chip SoCs introduced in the previous article using the benchmark CoreMark.

debian-riscv-litex-rocket
2022-02-05 / Last updated : 2022-02-18 admin FPGA

Booting RISC-V Debian in LiteX/Rocket on FPGA boards

We have succeeded in configuring SoCs with 64-bit RISC-V Rocket Chip using LiteX, and booting RISC-V Debian on two FPGA boards, a Qmtech Wukong board and a Digilent Nexys Video.

litex-vexriscv-tang-primer
2022-01-22 / Last updated : 2022-01-22 admin FPGA

Testing LiteX/VexRiscv on Sipeed Tang Primer

With the addition of initial support for Sipeed Tang Primer and Anlogic FPGA to LiteX, an SoC builder, we tried to create SoCs.

x11-usb-litex-vexriscv
2022-01-08 / Last updated : 2022-01-07 admin FPGA

Building an Octa-core 32-bit RISC-V PC on an FPGA board

We built an octa-core 32-bit RISC-V PC running the X Window System (X11) on the Qmtech Wukong board. The USB-connected keyboard and mouse use the Wireless Combo MK245 NANO from Logitech.

mic-array-maix-bit
2021-12-18 / Last updated : 2021-12-17 admin Maix Bit

Acoustic Beamforming using a Sipeed R6+1 Microphone Array

The Sipeed R6+1 microphone array can be used for sound source localization and beamforming by combining with Sipeed Maix Dock/Go/Bit. We calculated the pattern of this microphone array.

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