2023-05-27 / Last updated : 2023-05-26 admin RISC-V RISC-V Bit-Manipulation ISA-extensions In this article, we introduce the RISC-V Bit-Manipulation extension based on “RISC-V Bit-Manipulation ISA-extensions”, which was ratified in November 2021.
2023-05-13 / Last updated : 2023-05-12 admin Object Tracking DeepSORT: SORT with a Deep Association Metric In this article, we will discuss DeepSORT, which was published in 2017 and has influenced current multiple object tracking.
2023-04-22 / Last updated : 2023-04-21 admin Simulator GEMM based on the RISC-V Vector Extension (Part 3) We have created a GEMM-compatible floating-point matrix multiplication kernel based on the RISC-V Vector Extension and evaluated its performance using Ara’s RTL simulator.
2023-04-08 / Last updated : 2023-04-07 admin Object Tracking SORT: Simple Online and Realtime Tracking In this article, we will discuss SORT, Simple Online and Realtime Tracking, which was published in 2016 and has influenced the current multiple object tracking (MOT).
2023-03-25 / Last updated : 2023-03-25 admin Simulator GEMM based on the RISC-V Vector Extension (Part 2) We have evaluated vector load/store performance using Ara’s RTL simulator for transposed matrix support of matrix multiplication kernels based on the RISC-V Vector Extension.
2023-03-11 / Last updated : 2023-03-11 admin Simulator Vortex: OpenCL Compatible RISC-V Based GPGPU (Part 2) This article introduces the OpenCL support of Vortex, a RISC-V based open source GPGPU.
2023-02-25 / Last updated : 2023-03-11 admin Simulator GEMM based on the RISC-V Vector Extension (Part 1) We created double-, single- and half-precision floating-point matrix multiplication kernels based on the RISC-V Vector Extension and evaluated their performance using Ara’s RTL simulator.
2023-02-11 / Last updated : 2023-02-10 admin FPGA OpenBLAS on 32-bit RISC-V Multi-Core We made OpenBLAS compatible with 32-bit RISC-V and evaluated the performance of GEMM using an FPGA board with octa-core 32-bit RISC-V SoC.
2023-01-28 / Last updated : 2023-01-27 admin FPGA TFLite Micro on RISC-V Out-of-Order Core with Custom Instructions We have accelerated inference on Google’s TensorFlow Lite for Microcontrollers by adding SIMD instructions as custom instructions to NaxRiscv, a RISC-V out-of-order core.
2023-01-14 / Last updated : 2023-03-11 admin Simulator Vortex: OpenCL Compatible RISC-V Based GPGPU (Part 1) This article introduces an overview of Vortex, an open source RISC-V based GPGPU, and how to run the OpenCL program using the Vortex simulator.
