We have successfully built the gateware for RV64GC NaxRiscv, a RISC-V OoO CPU, for Digilent FPGA board and run Debian.
We have successfully run ONNX model on an FPGA board with a DNN accelerator Gemmini and a RISC-V CPU Rocket.
In order to utilize the RISC-V “V” vector extension (RVV), we have built programs using LLVM/Clang automatic vectorization and ran them on RTL simulator of Vicuna, which complies with the RVV specification v1.0.
We have successfully created gatewares for SoC of NaxRiscv, a RISC-V OoO CPU, for Digilent FPGA boards and run 32-bit Linux.
In this report, we propose a CNN called SAR ATR with verification support (SAVERS), which performs region-wise (i.e. coarse) segmentation and pixel-wise segmentation. SAVERS discriminates between target and non-target, and classifies multiple target classes and non-target class by coarse segmentation.
In this report, we propose a novel CNN for end-to-end ATR from SAR imagery. The CNN named VersNet inputs a SAR image of arbitrary sizes with multiple classes and multiple targets, and outputs a SAR ATR image representing the position, class, and pose of each detected target.
This report deals with translation invariance of convolutional neural networks (CNNs) for automatic target recognition (ATR) from synthetic aperture radar (SAR) imagery.