We have created a Verilator simulator for NaxRiscv, an out-of-order (OoO) superscalar RISC-V CPU. We ran CoreMark using the created simulator and confirmed 4.70 CoreMark/MHz as the nominal value of NaxRiscv.
We measured a performance of the multi-core 64-bit Rocket Chip SoCs introduced in the previous article using the benchmark CoreMark.
With the addition of initial support for Sipeed Tang Primer and Anlogic FPGA to LiteX, an SoC builder, we tried to create SoCs.
In this report, we propose a CNN called SAR ATR with verification support (SAVERS), which performs region-wise (i.e. coarse) segmentation and pixel-wise segmentation. SAVERS discriminates between target and non-target, and classifies multiple target classes and non-target class by coarse segmentation.
In this report, we propose a novel CNN for end-to-end ATR from SAR imagery. The CNN named VersNet inputs a SAR image of arbitrary sizes with multiple classes and multiple targets, and outputs a SAR ATR image representing the position, class, and pose of each detected target.
This report deals with translation invariance of convolutional neural networks (CNNs) for automatic target recognition (ATR) from synthetic aperture radar (SAR) imagery.