2023-02-11 / Last updated : 2023-02-10 admin FPGA OpenBLAS on 32-bit RISC-V Multi-Core We made OpenBLAS compatible with 32-bit RISC-V and evaluated the performance of GEMM using an FPGA board with octa-core 32-bit RISC-V SoC.
2023-01-28 / Last updated : 2023-01-27 admin FPGA TFLite Micro on RISC-V Out-of-Order Core with Custom Instructions We have accelerated inference on Google’s TensorFlow Lite for Microcontrollers by adding SIMD instructions as custom instructions to NaxRiscv, a RISC-V out-of-order core.
2022-12-24 / Last updated : 2023-01-25 admin FPGA Matrix Multiplication on FPGA with the RISC-V Vector Extension We have implemented Vicuna, an implementation of the RISC-V Vector Extension, on an FPGA board and evaluated the performance of the matrix multiplication kernel.
2022-12-10 / Last updated : 2023-01-25 admin FPGA OpenMP on FPGA with RISC-V Multi-Core Processor We have implemented a RISC-V multi-core processor on an FPGA board and evaluated the performance of the matrix multiplication kernel using OpenMP.
2022-11-19 / Last updated : 2022-12-10 admin FPGA TensorFlow Lite for Microcontrollers on RISC-V Out-of-Order Core We have successfully run Google’s TensorFlow Lite for Microcontrollers on an FPGA board implementing NaxRiscv, a RISC-V Out-of-Order core.
2022-09-24 / Last updated : 2022-12-10 admin FPGA Running Debian on FPGA with RISC-V Out-of-Order Core We have successfully built the gateware for RV64GC NaxRiscv, a RISC-V Out-of-Order core, for Digilent FPGA board and run Debian.
2022-08-06 / Last updated : 2022-09-23 admin FPGA Running ONNX Model on FPGA with Gemmini SoC We have successfully run ONNX model on an FPGA board with a DNN accelerator Gemmini and a RISC-V CPU Rocket.
2022-06-04 / Last updated : 2022-09-23 admin FPGA Running ResNet-50 on FPGA with Gemmini SoC We have successfully built a DNN system using the DNN accelerator Gemmini and the RISC-V CPU Rocket on a Digilent FPGA board and run ResNet-50.
2022-05-21 / Last updated : 2022-12-10 admin FPGA Running 32-bit Linux on FPGAs with RISC-V Out-of-Order Core We have successfully created gatewares for SoC of NaxRiscv, a RISC-V Out-of-Order core, for Digilent FPGA boards and run 32-bit Linux.
2022-02-19 / Last updated : 2022-12-09 admin FPGA Benchmarks in LiteX/Rocket on FPGA boards We measured a performance of the multi-core 64-bit Rocket Chip SoCs introduced in the previous article using the benchmark CoreMark.
