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Chipyard

an agile RISC-V SoC design framework

systolic-array
2022-08-06 / Last updated : 2022-09-23 admin FPGA

Running ONNX Model on FPGA with Gemmini SoC

We have successfully run ONNX model on an FPGA board with a DNN accelerator Gemmini and a RISC-V CPU Rocket.

systolic-array
2022-06-04 / Last updated : 2022-09-23 admin FPGA

Running ResNet-50 on FPGA with Gemmini SoC

We have successfully built a DNN system using the DNN accelerator Gemmini and the RISC-V CPU Rocket on a Digilent FPGA board and run ResNet-50.

benchmark-boom-simulator
2022-04-16 / Last updated : 2022-04-16 admin Simulator

Running CoreMark on SonicBOOM Simulator

We have created a simulator with the short-forwards branch (SFB) optimization of SonicBOOM, an out-of-order execution superscalar RISC-V CPU, and ran CoreMark.

systolic-array
2022-04-02 / Last updated : 2022-08-06 admin Simulator

Running Test Programs on Gemmini Simulators

We built an environment for Chipyard, a RISC-V SoC design framework, created simulators for Gemmini, a DNN accelerator, and ran the test programs gemmini-rocc-tests.

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