We built an environment for Chipyard, a RISC-V SoC design framework, created simulators for Gemmini, a DNN accelerator, and ran the test programs
Click here for related articles.
- Running Test Programs on Gemmini Simulators (this article)
- Running ResNet-50 on FPGA with Gemmini SoC
- Running ONNX Model on FPGA with Gemmini SoC
Chipyard is an agile RISC-V SoC design framework being developed by the University of California, Berkeley (UCB).
Chipyard includes RISC-V CPUs such as Rocket and BOOM, accelerators, and more.
Gemmini is one of the RTL generators included in Chipyard and can generate a systolic array based DNN accelerator.
You can configure an SoC by combining a RISC-V CPU Rocket or BOOM with a Gemmini.
Gemmini has several simulators. This time we have created the following simulators.
- Spike: Functional Simulator
- Verilator: Cycle-Accurate Simulator
The functional simulator Spike has an extension for Gemmini.
Running Test Programs on Spike
We ran ResNet-50 using Spike as follows:
$ cd $CHIPYARD_ROOT/generators/gemmini $ ./scripts/run-spike.sh resnet50 ... Prediction: 75 (score: 45) Prediction: 900 (score: 43) Prediction: 641 (score: 40) Prediction: 897 (score: 57) Total cycles: 4958105 (100%) Matmul cycles: 695733 (14%) Im2col cycles: 0 (0%) Conv cycles: 1769030 (35%) Pooling cycles: 0 (0%) Depthwise convolution cycles: 0 (0%) Res add cycles: 2398040 (48%) Other cycles: 95302 (1%) PASS
Running Test Programs on Verilator
conv_first_layer using Verilator as follows:
$ cd $CHIPYARD_ROOT/generators/gemmini $ ./scripts/run-verilator.sh conv_first_layer This emulator compiled with JTAG Remote Bitbang client. To enable, use +jtag_rbb_enable=1. Listening on port 33079 [UART] UART0 is here (stdin/stdout). Output dimension: 9 Randomize inputs... Randomize weights... Randomize bias... CPU conv... CPU conv took 2238789 cycles Flatten weights... Gemmini conv... Gemmini conv took 1796 cycles
We built an environment for Chipyard, created simulators for Gemmini, a DNN accelerator, and ran the test programs