2023-03-11 / Last updated : 2023-03-11 admin Simulator Vortex: OpenCL Compatible RISC-V Based GPGPU (Part 2) This article introduces the OpenCL support of Vortex, a RISC-V based open source GPGPU.
2023-02-25 / Last updated : 2023-03-11 admin Simulator GEMM based on the RISC-V Vector Extension (Part 1) We created double-, single- and half-precision floating-point matrix multiplication kernels based on the RISC-V Vector Extension and evaluated their performance using Ara’s RTL simulator.
2023-02-11 / Last updated : 2023-02-10 admin FPGA OpenBLAS on 32-bit RISC-V Multi-Core We made OpenBLAS compatible with 32-bit RISC-V and evaluated the performance of GEMM using an FPGA board with octa-core 32-bit RISC-V SoC.
2023-01-28 / Last updated : 2023-01-27 admin FPGA TFLite Micro on RISC-V Out-of-Order Core with Custom Instructions We have accelerated inference on Google’s TensorFlow Lite for Microcontrollers by adding SIMD instructions as custom instructions to NaxRiscv, a RISC-V out-of-order core.
2023-01-14 / Last updated : 2023-03-11 admin Simulator Vortex: OpenCL Compatible RISC-V Based GPGPU (Part 1) This article introduces an overview of Vortex, an open source RISC-V based GPGPU, and how to run the OpenCL program using the Vortex simulator.
2022-12-24 / Last updated : 2023-01-25 admin FPGA Matrix Multiplication on FPGA with the RISC-V Vector Extension We have implemented Vicuna, an implementation of the RISC-V Vector Extension, on an FPGA board and evaluated the performance of the matrix multiplication kernel.
2022-12-10 / Last updated : 2023-01-25 admin FPGA OpenMP on FPGA with RISC-V Multi-Core Processor We have implemented a RISC-V multi-core processor on an FPGA board and evaluated the performance of the matrix multiplication kernel using OpenMP.
2022-11-19 / Last updated : 2022-12-10 admin FPGA TensorFlow Lite for Microcontrollers on RISC-V Out-of-Order Core We have successfully run Google’s TensorFlow Lite for Microcontrollers on an FPGA board implementing NaxRiscv, a RISC-V Out-of-Order core.
2022-11-05 / Last updated : 2022-11-04 admin FPGA Applying the Tiny Matrix Extension to ML Inference We have accelerated machine learning (ML) model inference using a RISC-V processor that accelerates matrix multiplication at low resource cost.
2022-10-22 / Last updated : 2023-01-25 admin Simulator 1×1 Convolution based on the RISC-V Vector Extension We have created a 1×1 convolution kernel based on the RISC-V Vector Extension (RVV) and evaluated its performance using an RTL simulator.
