2022-06-18 / Last updated : 2022-06-17 admin Simulator Running Auto-Vectorized Program on RISC-V Vector RTL Simulator In order to utilize the RISC-V “V” vector extension (RVV), we have built programs using LLVM/Clang automatic vectorization and ran them on RTL simulator of Vicuna, which complies with the RVV specification v1.0.
2022-06-04 / Last updated : 2022-06-17 admin FPGA Running ResNet-50 on FPGA with Gemmini SoC We have successfully built a DNN system using the DNN accelerator Gemmini and the RISC-V CPU Rocket on a Digilent FPGA board and run ResNet-50.
2022-05-21 / Last updated : 2022-05-20 admin FPGA Running 32-bit Linux on FPGAs with RISC-V OoO CPU We have successfully created gatewares for SoC of NaxRiscv, a RISC-V OoO CPU, for Digilent FPGA boards and run 32-bit Linux.
2022-04-16 / Last updated : 2022-04-16 admin Simulator Running CoreMark on SonicBOOM Simulator We have created a simulator with the short-forwards branch (SFB) optimization of SonicBOOM, an out-of-order execution superscalar RISC-V CPU, and ran CoreMark.
2022-04-02 / Last updated : 2022-04-01 admin Simulator Running Test Programs on Gemmini Simulators We built an environment for Chipyard, a RISC-V SoC design framework, created simulators for Gemmini, a DNN accelerator, and ran the test programs gemmini-rocc-tests.
2022-03-19 / Last updated : 2022-05-20 admin Simulator Running CoreMark on NaxRiscv Simulator We have created a Verilator simulator for NaxRiscv, an out-of-order (OoO) superscalar RISC-V CPU. We ran CoreMark using the created simulator and confirmed 4.70 CoreMark/MHz as the nominal value of NaxRiscv.
2022-03-05 / Last updated : 2022-05-20 admin FPGA Building an ML Accelerator using CFU Playground (Part 1) We have built a machine learning (ML) accelerator on an Arty A7-35T using CFU Playground. In part 1, we have accelerated the inference of the Person Detection int 8 model.
2022-02-19 / Last updated : 2022-05-30 admin FPGA Benchmarks in LiteX/Rocket on FPGA boards We measured a performance of the multi-core 64-bit Rocket Chip SoCs introduced in the previous article using the benchmark CoreMark.
2022-02-05 / Last updated : 2022-02-18 admin FPGA Booting RISC-V Debian in LiteX/Rocket on FPGA boards We have succeeded in configuring SoCs with 64-bit RISC-V Rocket Chip using LiteX, and booting RISC-V Debian on two FPGA boards, a Qmtech Wukong board and a Digilent Nexys Video.
2022-01-22 / Last updated : 2022-01-22 admin FPGA Testing LiteX/VexRiscv on Sipeed Tang Primer With the addition of initial support for Sipeed Tang Primer and Anlogic FPGA to LiteX, an SoC builder, we tried to create SoCs.
