2022-06-18 / Last updated : 2022-06-17 admin Simulator Running Auto-Vectorized Program on RISC-V Vector RTL Simulator In order to utilize the RISC-V “V” vector extension (RVV), we have built programs using LLVM/Clang automatic vectorization and ran them on RTL simulator of Vicuna, which complies with the RVV specification v1.0.
2022-04-16 / Last updated : 2022-04-16 admin Simulator Running CoreMark on SonicBOOM Simulator We have created a simulator with the short-forwards branch (SFB) optimization of SonicBOOM, an out-of-order execution superscalar RISC-V CPU, and ran CoreMark.
2022-04-02 / Last updated : 2022-04-01 admin Simulator Running Test Programs on Gemmini Simulators We built an environment for Chipyard, a RISC-V SoC design framework, created simulators for Gemmini, a DNN accelerator, and ran the test programs gemmini-rocc-tests.
2022-03-19 / Last updated : 2022-05-20 admin Simulator Running CoreMark on NaxRiscv Simulator We have created a Verilator simulator for NaxRiscv, an out-of-order (OoO) superscalar RISC-V CPU. We ran CoreMark using the created simulator and confirmed 4.70 CoreMark/MHz as the nominal value of NaxRiscv.
