2022-08-20 / Last updated : 2022-08-21 admin Simulator Matrix Multiplication based on the RISC-V Vector Extension We have created a matrix multiplication kernel based on the RISC-V Vector Extension (RVV) and evaluated its performance using an RTL simulator.
2022-07-16 / Last updated : 2022-09-24 admin Simulator Benchmarks on RV64GC RISC-V OoO Simulator Since the RISC-V out-of-order (OoO) CPU NaxRiscv now supports RV[32|64]GC, we have created an RV64GC simulator and ran the benchmarks CoreMark, Dhrystone, and Whetstone.
2022-06-18 / Last updated : 2022-06-17 admin Simulator Running Auto-Vectorized Program on RISC-V Vector RTL Simulator In order to utilize the RISC-V “V” vector extension (RVV), we have built programs using LLVM/Clang automatic vectorization and ran them on RTL simulator of Vicuna, which complies with the RVV specification v1.0.
2022-04-16 / Last updated : 2022-04-16 admin Simulator Running CoreMark on SonicBOOM Simulator We have created a simulator with the short-forwards branch (SFB) optimization of SonicBOOM, an out-of-order execution superscalar RISC-V CPU, and ran CoreMark.
2022-04-02 / Last updated : 2022-08-06 admin Simulator Running Test Programs on Gemmini Simulators We built an environment for Chipyard, a RISC-V SoC design framework, created simulators for Gemmini, a DNN accelerator, and ran the test programs gemmini-rocc-tests.
2022-03-19 / Last updated : 2022-09-24 admin Simulator Benchmarks on RISC-V OoO Simulator We have created a simulator for NaxRiscv, an out-of-order (OoO) RISC-V CPU, and ran the benchmarks CoreMark and Dhrystone.
